1. Field of the Invention
The present invention is related to computer peripheral device I/O operations, and more particularly to an I/O hub and its method of operation that provide for atomic I/O operations controlled by non-atomic processor operations.
2. Description of Related Art
Input/Output (I/O) operations between processors and peripheral devices such as storage subsystems, network interfaces and co-processing units that are connected to the processors via a hub or other bus interface have traditionally been performed using commands or transactions that do not modify I/O device storage in an uninterruptable (atomic) manner. Examples of such I/O device buses are peripheral component interconnect (PCI), including serial express versions such as PCI EXPRESS, HYPERTRANSPORT buses and the like. (PCI and PCI EXPRESS are trademarks of PCI-SIG, HYPERTRANSPORT is a trademark of Advanced Microdevices, Inc.) While some systems, such as INTEL Architecture (IA-32, IA64) processors provide bus locking or specific atomic operations at the processor bus level so that system integrity is maintained during operations by multiple processors, operations that are directed at devices and reflected on I/O device buses have typically not been atomic operations. (INTEL is a trademark of Intel Corporation.) Other architectures such as POWER processors have no atomic operations. (POWER is a trademark of International Business Machines Corporation.) The nature of “atomic” operations is that the instruction is complete in a single operation on the bus and the operation is non-interruptible, so that no other bus activity is permitted while the operation is executed.
Recently, atomic operations directed to device buses have been proposed that will permit, for example, faster interleave of interactions with devices such as coprocessors and dedicated hardware that accelerates certain functions within a processing system. The operations are atomic with respect to multiprocessing within the device, which may contain one or more processors, and/or which may perform simultaneous operations on data within device memory.
The support of atomic operations provides that multiple operations within the device can be performed while retaining data queues and operation results within the device memory without other synchronization mechanisms that typically only permit exclusive use of the device for one operation at a time or restrictive management of operation sequencing. In order to facilitate such atomic operations, atomic I/O operations are supported by the I/O device interconnect and devices connected by the I/O device interconnect. In processor architectures already supporting the issue of atomic operations on their system interconnects, those atomic operations can be used with some modification to operate on memory-mapped I/O in the devices. The processors cause an atomic operation to be issued to system interconnect, translated from the system interconnect to the I/O device, and in response, the device performs the atomic operation before control is relinquished, ensuring complete system integrity during the operation.
However, there are several drawbacks to the implementation of such systems. First, while all practical multiprocessor systems support atomic operations in some manner, not all multiprocessor systems do so by using system interconnects and instruction set architectures (ISAs) that support atomic operations directly. Therefore, inclusion of atomic I/O operations may not be practical or may be incompatible with a particular processor or system interconnect architecture. Second, since the device at which an atomic I/O operation is directed determines the completion of the atomic operation, interconnect under-utilization penalties can be very high for atomic I/O operations, since the atomic operation requires at least some system interconnect exclusivity while the atomic operation is performed. Finally, even if a particular ISA directly supports atomic operations, the atomic operations that the device is designed to use may include operations that are not present in the particular ISA.
Therefore, it would be desirable to provide a method and system that can issue and perform atomic operations on an I/O device interconnect without requiring the processor architecture to include specific atomic operations, without requiring the processor to support each atomic operation that may be required by any I/O device, and without incurring penalties associated with system interconnect exclusivity while an atomic I/O operation is performed.